ビットマップインデックスに基づくデータ解析のためのハードウェアシステムに関する研究

Recent years have witnessed a massive growth of global data generated from web services, social media networks, and science experiments, as well as the 　“tsunami" of Internet-of-Things devices. According to a Cisco forecast, total data center traffic is projected to hit 15.3 zettabytes (ZB) by the end of 2020. Gaining insight into a vast amount of data is highly important because valuable data are the driving force for business decisions and processes, as well as scientists\u27 exploration and discovery.To facilitate analytics, data are usually indexed in advance. Depending on the workloads, such as online transaction processing (OLTP) workloads and online analytics processing (OLAP) workloads, several indexing frameworks have been proposed. Specifically, B+-tree and hash are two common indexing methods in OLTP, where the number of querying and updating processes are nearly similar. Unlike OLTP, OLAP concentrates on querying in a huge historical storage, where updating processes are irregular. Most queries in OLAP are also highly complex and involve aggregations, while the execution time is often limited. To address these challenges, a bitmap index (BI) was proposed and has been proven as a promising candidate for OLAP-like workloads.A BI is a bit-level matrix, whose number of rows and columns are the length and cardinality of the datasets, respectively. With a BI, answering multi-dimensional queries becomes a series of bitwise operators, e.g. AND, OR, XOR, and NOT, on bit columns. As a result, a BI has proven profitable for solving complex queries in large enterprise databases and scientific databases. More significantly, because of the usage of low-hardware logical operators, a BI appears to be suitable for advanced parallel-processing platforms, such as multi-core CPUs, graphics processing units (GPUs), field-programmable logic arrays (FPGAs), and application-specific integrated circuits (ASIC).Modern FPGAs and ASICs have become increasingly important in data analytics because they can confront both data-intensive and computing-intensive tasks effectively. Furthermore, FPGAs and ASICs can provide higher energy efficiency, compared to CPUs and GPUs. As a result, since 2010, Microsoft has been working on the so-called Catapult project, where FPGAs were integrated into datacenter servers to accelerate their search engine as well as AI applications. In 2016, Oracle for the first time introduced SPARC S7 and M7 processors that are used for accelerating the OLTP databases. Nonetheless, a study on the feasibility of BI-based analytics systems using FPGAs and ASICs has not yet been developed.This dissertation, therefore, focuses on implementing the data analytics systems, in both FPGAs and ASICs, using BI. The advantages of the proposed systems include scalability, low data input/output cost, high processing throughput, and high energy efficiency. Three main modules are proposed: (1) a BI creator that indexes the given records by a list of keys and outputs the BI vectors to the external memory; (2) a BI-based query processor that employs the given BI vectors to answer users\u27 queries and outputs the results to the external memory; and (3) an BI encoder that returns the positions of one-bits of bitmap results to the external memory. Six hardware systems based on those three modules are implemented in an FPGA in advance for functional verification and then partially in two ASICs|180-nm bulk complementary metal-oxide-semiconductor (CMOS) and 65-nm Silicon-On-Thin-Buried-Oxide (SOTB) CMOS technology―for physical design verification. Based on the experimental results, these proposed systems outperform other CPU-based and GPU-based designs, especially in terms of energy efficiency.電気通信大学201

Identify and predict incorrect prices by Machine Learning Model

Electronic commerce (e-commerce) brings huge advantages to businesses for selling products through multiple online shops. However, companies have difficulties in supervising the prices of products set by different retail shops on e-commerce platforms. Addressing these difficulties, we suggest a method to identify and predict products that sell at incorrect prices using a machine learning model combined price analysis. The study uses four machine learning models: K-nearest Neighbor (KNN), Random Forest (RF), Support Vector Machine (SVM), and Multinomial Naive Bayes (MNB) and two text-based information extraction methods: BoW and TF-IDF to find to the best method. The research results show that the RF model and text-based information extraction method by the BoW provide more average accuracy than other specific models, when experimenting on the filter dataset the average accuracy after 10 runs are RF: 98.06%, SVM: 83.92%, MNB: 92.21%, KNN: 94.06%. Experimental results on the product dataset have an accuracy of RF: 83.02%, SVM: 55%, MNB: 79.33%, KNN: 79.36%

Simple thermal-electrical model of photovoltaic panels with cooler-integrated sun tracker

This paper presents a simple thermal-electrical model of a photovoltaic panel with a cooler-integrated sun tracker. Based on the model and obtained weather data, we analyzed the improved overall efficiency in a year as well as the performance in each typical weather case for photovoltaic panels with fixed-tilt systems with a tilt angle equal to latitude, fixed-tilt systems with cooler, a single-axis sun tracker, and a cooler-integrated single-axis sun tracker. The results show that on a sunny summer day with few clouds, the performance of the photovoltaic panels with the proposed system improved and reached 32.76% compared with the fixed-tilt systems. On a sunny day with clouds in the wet, rainy season, because of the low air temperature and the high wind speed, the photovoltaic panel temperature was lower than the cooler’s initial set temperature; the performance of the photovoltaic panel with the proposed system improved by 12.55% compared with the fixed-tilt system. Simulation results show that, over one year, the overall efficiency of the proposed system markedly improved by 16.35, 13.03, and 3.68% compared with the photovoltaic panel with the fixed-tilt system, the cooler, and the single-axis sun tracker, respectively. The simulation results can serve as a premise for future experimental models

PROBLEMS OF ENGLISH STUDIES STUDENTS ON LEARNING PHONOLOGY AND SUGGESTIONS, CAN THO UNIVERSITY, VIETNAM

The writers were concerned by the phonological challenges encountered by students of the Schools of Foreign Languages, Can Tho University. Foreign language majors are often difficult, and theory is quite tackled, which has caused many serious problems for students. This is no exception for students majoring in English Studies, at Can Tho University in the process of approaching the subject "Introduction to English Phonology". This study was conducted to clarify the phonological challenges that students at Can Tho University are facing, as well as suggest solutions to the problem of phonology learners. Using data from Google Questionnaire Forms, the research conducted an error analysis of 103 English majors who studied the subject. Based on the phonological problems, certain remedial activities were planned for the students, which helped improve their study process phonological problems considerably.   Article visualizations

A FLEXIBLE HIGH-BANDWIDTH LOW-LATENCY MULTI-PORT MEMORY CONTROLLER

Multi-port memory controllers (MPMCs) have become increasingly important in many modern applications due to the tremendous growth in bandwidth requirement. Many approaches so far have focused on improving either the memory access latency or the bandwidth utilization for specific applications. Moreover, the application systems are likely to require certain adjustments to connect with an MPMC, since the MPMC interface is limited to a single-clock and single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dualport FIFOs at each port, so any multi-clock multi-data-width application system can connect to an MPMC without requiring extra resources. Secondly, memory access latency is significantly reduced because parallel FIFOs temporarily keep the data transfer between the application system and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be properly configured by updating several internal configuration registers. The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth utilization is approximately 93.2% of the theoretical bandwidth, and the access latency is minimized as compared to previous designs

Two Spot Coupled Ring Resonators

Abstract. We consider a model of two coupled ring waveguides with constant linear gain and nonlinear absorption with space-dependent coupling. This system can be implemented in various physical situations as optical waveguides, atomic Bose-Einstein condensates, polarization condensates, etc. It is described by two coupled nonlinear Schrödinger equation. For numerical simulations, we take local two-gaussian coupling.It is found in our previous papers that, depending on the values of involved parameters, we can obtain several interesting nonlinear phenomena, which include spontaneous symmetry breaking, modulational instability leading to generation of stable circular flows with various vorticities, stable inhomogeneous states with interesting structure of currents flowing between rings, as well as dynamical regimes having signatures of chaotic behavior. This research will be associated with experimental investigation planned in Freie Universität Berlin, in the group of prof. Michael Giersig